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ACTS573T
Data Sheet July 1999 File Number
4613.1
Radiation Hardened Octal Three-State Transparent Latch
Intersil's Satellite Applications FlowTM (SAF) devices are fully tested and guaranteed to 100kRAD total dose. These QML Class T devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. The Intersil ACTS573T is a Radiation Hardened Octal Transparent Latch with an active low output enable. The outputs are transparent to the inputs when the latch enable (LE) is High. When the latch goes low the data is latched. The output enable controls the three-state outputs. When the output enable pins (OE) are high the output is in a high impedance state. The latch operation is independent of the state of output enable.
Features
* QML Class T, Per MIL-PRF-38535 * Radiation Performance - Gamma Dose () 1 x 105 RAD(Si) - Latch-Up Free Under Any Conditions - Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day (Typ) - SEU LET Threshold . . . . . . . . . . . . .>100 MEV-cm2/mg * 1.25 Micron Radiation Hardened SOS CMOS * Significant Power Reduction Compared to ALSTTL Logic * DC Operating Voltage Range . . . . . . . . . . . . 4.5V to 5.5V * Input Logic Levels - VIL = 0.8V Max - VIH = VCC/2 Min * Fast Propagation Delay . . . . . . . . 18ns (Max), 12ns (Typ)
Specifications
Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the ACTS573T are contained in SMD 5962-96725. A "hot-link" is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp Intersil's Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp
Pinouts
ACTS573T (SBDIP), CDIP2-T20 TOP VIEW
OE D0 D1 D2 D3 D4 D5 D6 1 2 3 4 5 6 7 8 9 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 LE
Ordering Information
ORDERING INFORMATION 5962R9672502TRC 5962R9672502TXC PART NUMBER ACTS573DTR-02 ACTS573KTR-02 TEMP. RANGE (oC) -55 to 125 -55 to 125
D7
GND 10
ACTS573T (FLATPACK), CDFP4-F20 TOP VIEW
OE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LE
NOTE: Minimum order quantity for -T is 150 units through
distribution, or 450 units direct.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
ACTS573T Functional Diagram
1 OF 8 IDENTICAL CIRCUITS
VCC LE p Dn n LE LE p n LE OE n VSS Qn OE p
COMMON CONTROLS
LE LE
LE OE OE
OE
TRUTH TABLE OE L L L L H LE H H L L X DATA H L l h X OUTPUT H L L H Z
NOTE: L = Low Logic Level, H = High Logic Level, X = Don't Care, Z = High Impedance, l = Low Voltage Level Prior to High-to-Low Latch Enable Transition, h = High Voltage Level Prior to High-to-Low Latch Enable Transition.
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ACTS573T Die Characteristics
DIE DIMENSIONS: (2600m x 2600m x 533m 51m) 102 x 102 x 21mils 2mil METALLIZATION: Type: Al Si Cu Thickness: 10kA 2kA SUBSTRATE POTENTIAL: Unbiased (Silicon on Sapphire) Bond Pad #20 First BACKSIDE FINISH: Sapphire PASSIVATION: Type: Silox (SiO2) Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 190 PROCESS: CMOS SOS
Metallization Mask Layout
ACTS573T
(20) VCC
(19) Q0
(18) Q1
(1) OE
(3) D1
(2) D0
D2 (4) D3 (5) NC
(17) Q2 (16) Q3 NC
NC D4 (6) D5 (7)
NC (15) Q4 (14) Q5
GND (10)
LE (11)
D6 (8)
D7 (9)
Q7 (12)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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Q6 (13)

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